Apply hekate 5.2.1 and gcc 10 changes, -fno-inline
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shchmue
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64 changed files with 4676 additions and 3360 deletions
171
source/gfx/di.h
171
source/gfx/di.h
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2018 naehrwert
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* Copyright (c) 2018 CTCaer
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* Copyright (c) 2018-2019 CTCaer
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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@ -24,6 +24,21 @@
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/*! Display registers. */
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#define _DIREG(reg) ((reg) * 4)
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// Display controller scratch registers.
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#define DC_D_WINBUF_DD_SCRATCH_REGISTER_0 0xED
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#define DC_D_WINBUF_DD_SCRATCH_REGISTER_1 0xEE
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#define DC_T_WINBUF_TD_SCRATCH_REGISTER_0 0x16D
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#define DC_T_WINBUF_TD_SCRATCH_REGISTER_1 0x16E
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#define DC_COM_SCRATCH_REGISTER_A 0x325
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#define DC_COM_SCRATCH_REGISTER_B 0x326
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#define DC_A_WINBUF_AD_SCRATCH_REGISTER_0 0xBED
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#define DC_A_WINBUF_AD_SCRATCH_REGISTER_1 0xBEE
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#define DC_B_WINBUF_BD_SCRATCH_REGISTER_0 0xDED
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#define DC_B_WINBUF_BD_SCRATCH_REGISTER_1 0xDEE
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#define DC_C_WINBUF_CD_SCRATCH_REGISTER_0 0xFED
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#define DC_C_WINBUF_CD_SCRATCH_REGISTER_1 0xFEE
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// DC_CMD non-shadowed command/sync registers.
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#define DC_CMD_GENERAL_INCR_SYNCPT 0x00
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#define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x01
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@ -50,6 +65,7 @@
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#define PM0_ENABLE (1 << 16)
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#define PM1_ENABLE (1 << 18)
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#define DC_CMD_INT_STATUS 0x37
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#define DC_CMD_INT_MASK 0x38
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#define DC_CMD_INT_ENABLE 0x39
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@ -62,11 +78,13 @@
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#define WIN_A_ACT_REQ (1 << 1)
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#define WIN_B_ACT_REQ (1 << 2)
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#define WIN_C_ACT_REQ (1 << 3)
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#define WIN_D_ACT_REQ (1 << 4)
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#define CURSOR_ACT_REQ (1 << 7)
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#define GENERAL_UPDATE (1 << 8)
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#define WIN_A_UPDATE (1 << 9)
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#define WIN_B_UPDATE (1 << 10)
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#define WIN_C_UPDATE (1 << 11)
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#define WIN_D_UPDATE (1 << 12)
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#define CURSOR_UPDATE (1 << 15)
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#define NC_HOST_TRIG (1 << 24)
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@ -74,15 +92,38 @@
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#define WINDOW_A_SELECT (1 << 4)
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#define WINDOW_B_SELECT (1 << 5)
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#define WINDOW_C_SELECT (1 << 6)
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#define WINDOW_D_SELECT (1 << 7)
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#define DC_CMD_REG_ACT_CONTROL 0x043
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// DC_D_WIN_DD window D instance of DC_WIN
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#define DC_D_WIN_DD_WIN_OPTIONS 0x80
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#define DC_D_WIN_DD_COLOR_DEPTH 0x83
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#define DC_D_WIN_DD_POSITION 0x84
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#define DC_D_WIN_DD_SIZE 0x85
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#define DC_D_WIN_DD_LINE_STRIDE 0x8A
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#define DC_D_WIN_DD_BLEND_LAYER_CONTROL 0x96
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#define DC_D_WIN_DD_BLEND_MATCH_SELECT 0x97
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#define DC_D_WIN_DD_BLEND_ALPHA_1BIT 0x99
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// DC_D_WINBUF_DD window D instance of DC_WINBUF
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#define DC_D_WINBUF_DD_START_ADDR 0xC0
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#define DC_D_WINBUF_DD_ADDR_H_OFFSET 0xC6
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#define DC_D_WINBUF_DD_ADDR_V_OFFSET 0xC8
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#define DC_D_WINBUF_DD_START_ADDR_HI 0xCD
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#define DC_D_WINBUF_DD_MEMFETCH_CONTROL 0xEB
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// DC_T_WIN_TD macro for using DD defines.
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#define _DC_T(reg) ((reg) + 0x80)
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// DC_COM non-shadowed registers.
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#define DC_COM_CRC_CONTROL 0x300
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#define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
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#define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
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#define DC_COM_DSC_TOP_CTL 0x33E
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// DC_DISP shadowed registers.
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#define DC_DISP_DISP_WIN_OPTIONS 0x402
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#define HDMI_ENABLE (1 << 30)
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#define DSI_ENABLE (1 << 29)
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@ -161,6 +202,32 @@
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#define DE_CONTROL_EARLY (3 << 2)
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#define DE_CONTROL_ACTIVE_BLANK (4 << 2)
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// Cursor configuration registers.
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#define DC_DISP_CURSOR_FOREGROUND 0x43C
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#define DC_DISP_CURSOR_BACKGROUND 0x43D
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#define CURSOR_COLOR(r,g,b) (((r) & 0xFF) | (((g) & 0xFF) << 8) | (((b) & 0xFF) << 16))
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#define DC_DISP_CURSOR_START_ADDR 0x43E
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#define CURSOR_CLIPPING(w) ((w) << 28)
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#define CURSOR_CLIP_WIN_A 1
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#define CURSOR_CLIP_WIN_B 2
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#define CURSOR_CLIP_WIN_C 3
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#define CURSOR_SIZE_32 (0 << 24)
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#define CURSOR_SIZE_64 (1 << 24)
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#define CURSOR_SIZE_128 (2 << 24)
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#define CURSOR_SIZE_256 (3 << 24)
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#define DC_DISP_CURSOR_POSITION 0x440
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#define DC_DISP_CURSOR_START_ADDR_HI 0x4EC
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#define DC_DISP_BLEND_CURSOR_CONTROL 0x4F1
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#define CURSOR_BLEND_2BIT (0 << 24)
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#define CURSOR_BLEND_R8G8B8A8 (1 << 24)
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#define CURSOR_BLEND_SRC_FACTOR(n) ((n) << 8)
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#define CURSOR_BLEND_DST_FACTOR(n) ((n) << 16)
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#define CURSOR_BLEND_ZRO 0
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#define CURSOR_BLEND_K1 1
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#define CURSOR_BLEND_NK1 2
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// End of cursor cfg regs.
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#define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
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#define DC_DISP_SD_BL_PARAMETERS 0x4D7
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#define DC_DISP_SD_BL_CONTROL 0x4DC
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@ -187,6 +254,13 @@
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#define CSC_ENABLE (1 << 18)
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#define WIN_ENABLE (1 << 30)
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#define DC_WIN_BUFFER_CONTROL 0x702
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#define BUFFER_CONTROL_HOST 0
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#define BUFFER_CONTROL_VI 1
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#define BUFFER_CONTROL_EPP 2
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#define BUFFER_CONTROL_MPEGE 3
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#define BUFFER_CONTROL_SB2D 4
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#define DC_WIN_COLOR_DEPTH 0x703
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#define WIN_COLOR_DEPTH_P1 0x0
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#define WIN_COLOR_DEPTH_P2 0x1
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@ -211,8 +285,9 @@
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#define WIN_COLOR_DEPTH_YCbCr422RA 0x18
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#define WIN_COLOR_DEPTH_YUV422RA 0x19
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#define DC_WIN_BUFFER_CONTROL 0x702
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#define DC_WIN_POSITION 0x704
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#define H_POSITION(x) (((x) & 0xFfff) << 0)
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#define V_POSITION(x) (((x) & 0x1fff) << 16)
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#define DC_WIN_SIZE 0x705
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#define H_SIZE(x) (((x) & 0x1fff) << 0)
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@ -234,6 +309,42 @@
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#define UV_LINE_STRIDE(x) (((x) & 0xffff) << 16)
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#define DC_WIN_DV_CONTROL 0x70E
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#define DC_WINBUF_BLEND_LAYER_CONTROL 0x716
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#define WIN_K1(x) (((x) & 0xff) << 8)
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#define WIN_K2(x) (((x) & 0xff) << 16)
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#define WIN_BLEND_ENABLE (0 << 24)
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#define WIN_BLEND_BYPASS (1 << 24)
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#define DC_WINBUF_BLEND_MATCH_SELECT 0x717
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#define WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ZERO (0 << 0)
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#define WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_ONE (1 << 0)
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#define WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1 (2 << 0)
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#define WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_DST (3 << 0)
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#define WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_NEG_K1_TIMES_DST (4 << 0)
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#define WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_SRC (5 << 0)
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#define WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ZERO (0 << 4)
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#define WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_ONE (1 << 4)
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#define WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1 (2 << 4)
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#define WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K2 (3 << 4)
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#define WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_K1_TIMES_DST (4 << 4)
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#define WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_DST (5 << 4)
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#define WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_SRC (6 << 4)
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#define WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1 (7 << 4)
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#define WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_ZERO (0 << 8)
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#define WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K1 (1 << 8)
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#define WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2 (2 << 8)
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#define WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO (0 << 12)
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#define WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ONE (1 << 12)
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#define WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_NEG_K1_TIMES_SRC (2 << 12)
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#define WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_K2 (3 << 12)
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#define DC_WINBUF_BLEND_ALPHA_1BIT 0x719
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#define WIN_ALPHA_1BIT_WEIGHT0(x) (((x) & 0xff) << 0)
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#define WIN_ALPHA_1BIT_WEIGHT1(x) (((x) & 0xff) << 8)
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/*! The following registers are A/B/C shadows of the 0xBC0/0xDC0/0xFC0 registers (see DISPLAY_WINDOW_HEADER). */
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#define DC_WINBUF_START_ADDR 0x800
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#define DC_WINBUF_ADDR_H_OFFSET 0x806
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@ -336,6 +447,7 @@
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#define DSI_PAD_CONTROL_CD 0x4C
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#define DSI_VIDEO_MODE_CONTROL 0x4E
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#define DSI_CMD_PKT_VID_ENABLE 1
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#define DSI_PAD_CONTROL_1 0x4F
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#define DSI_PAD_CONTROL_2 0x50
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@ -349,7 +461,57 @@
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#define DSI_PAD_CONTROL_4 0x52
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#define DSI_INIT_SEQ_DATA_15 0x5F
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#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 0x60
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/*! MIPI registers. */
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#define MIPI_CAL_MIPI_CAL_CTRL (0x00 / 0x4)
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#define MIPI_CAL_CIL_MIPI_CAL_STATUS (0x08 / 0x4)
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#define MIPI_CAL_CILA_MIPI_CAL_CONFIG (0x14 / 0x4)
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#define MIPI_CAL_CILB_MIPI_CAL_CONFIG (0x18 / 0x4)
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#define MIPI_CAL_CILC_MIPI_CAL_CONFIG (0x1C / 0x4)
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#define MIPI_CAL_CILD_MIPI_CAL_CONFIG (0x20 / 0x4)
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#define MIPI_CAL_CILE_MIPI_CAL_CONFIG (0x24 / 0x4)
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#define MIPI_CAL_CILF_MIPI_CAL_CONFIG (0x28 / 0x4)
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#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG (0x38 / 0x4)
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#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG (0x3C / 0x4)
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#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG (0x40 / 0x4)
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#define MIPI_CAL_DSID_MIPI_CAL_CONFIG (0x44 / 0x4)
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#define MIPI_CAL_MIPI_BIAS_PAD_CFG0 (0x58 / 0x4)
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#define MIPI_CAL_MIPI_BIAS_PAD_CFG1 (0x5C / 0x4)
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#define MIPI_CAL_MIPI_BIAS_PAD_CFG2 (0x60 / 0x4)
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#define MIPI_CAL_DSIA_MIPI_CAL_CONFIG_2 (0x64 / 0x4)
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#define MIPI_CAL_DSIB_MIPI_CAL_CONFIG_2 (0x68 / 0x4)
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#define MIPI_CAL_DSIC_MIPI_CAL_CONFIG_2 (0x70 / 0x4)
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#define MIPI_CAL_DSID_MIPI_CAL_CONFIG_2 (0x74 / 0x4)
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/*! MIPI CMDs. */
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#define MIPI_DSI_DCS_SHORT_WRITE 0x05
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#define MIPI_DSI_DCS_READ 0x06
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#define MIPI_DSI_DCS_SHORT_WRITE_PARAM 0x15
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#define MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE 0x37
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#define MIPI_DSI_DCS_LONG_WRITE 0x39
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/*! MIPI DCS CMDs. */
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#define MIPI_DCS_GET_DISPLAY_ID 0x04
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#define MIPI_DCS_ENTER_SLEEP_MODE 0x10
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#define MIPI_DCS_EXIT_SLEEP_MODE 0x11
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#define MIPI_DCS_SET_DISPLAY_ON 0x29
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/* Switch Panels:
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* [10] 81 [26]: JDI LPM062M326A
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* [10] 96 [09]: JDI LAM062M109A
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* [20] 93 [0F]: InnoLux P062CCA-AZ1 (Rev A1)
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* [20] XX [10]: InnoLux P062CCA-AZ2 [UNCONFIRMED ID]
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* [30] 94 [0F]: AUO A062TAN01 (59.06A33.001)
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* [30] XX [10]: AUO A062TAN02 (59.06A33.002) [UNCONFIRMED ID]
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*/
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enum
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{
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PANEL_JDI_LPM062M = 0x10,
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PANEL_INL_P062CCA_AZ1 = 0x0F20,
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PANEL_AUO_A062TAN01 = 0x0F30,
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PANEL_INL_P062CCA_AZ2 = 0x1020,
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PANEL_AUO_A062TAN02 = 0x1030
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};
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void display_init();
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void display_backlight_pwm_init();
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@ -364,5 +526,8 @@ void display_backlight_brightness(u32 brightness, u32 step_delay);
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/*! Init display in full 1280x720 resolution (B8G8R8A8, line stride 768, framebuffer size = 1280*768*4 bytes). */
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u32 *display_init_framebuffer();
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void display_init_cursor(void *crs_fb, u32 size);
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void display_set_pos_cursor(u32 x, u32 y);
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void display_deinit_cursor();
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#endif
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